Added Software projects

git-svn-id: file:///srv/dev-disk-by-uuid-17e88007-4d0c-45e0-8757-cacfcc458630/repositories/svn/Diplomarbeit@55 9fe90eed-be63-e94b-8204-d34ff4c2ff93
2008-12-23 10:34:08 +00:00
parent ee5a771818
commit 373a8c32b2
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+/******************************************************************************
+ *
+ * $RCSfile: $
+ * $Revision: $
+ *
+ * This module implements the ISRs for the UARTs on the LPC ARMs.
+ * Copyright 2004, R O SoftWare
+ * No guarantees, warrantees, or promises, implied or otherwise.
+ * May be used for hobby or commercial purposes provided copyright
+ * notice remains intact.
+ *
+ * Modified by Martin Thomas for LPC23xx 24xx
+ *****************************************************************************/
+#include "app_types.h"
+#include "LPC_REGS.h"
+
+#include "uart2.h"
+#include "uart2ISR.h"
+#include "armVIC.h"
+
+extern uint8_t  uart2_rx_buffer[UART2_RX_BUFFER_SIZE];
+extern uint16_t uart2_rx_insert_idx, uart2_rx_extract_idx;
+extern uint8_t  uart2_tx_buffer[UART2_TX_BUFFER_SIZE];
+extern uint16_t uart2_tx_insert_idx, uart2_tx_extract_idx;
+extern int      uart2_tx_running;
+
+extern int uart2TxFinished(void);
+
+/******************************************************************************
+ *
+ * Function Name: uart2ISR()
+ *
+ * Description:
+ *    This function implements the ISR for UART2.
+ *
+ * Calling Sequence: 
+ *    void
+ *
+ * Returns:
+ *    void
+ *
+ *****************************************************************************/
+void uart2ISR(void)
+{
+  uint8_t iid;
+
+  // perform proper ISR entry so thumb-interwork works properly
+  ISR_ENTRY();
+
+  // loop until not more interrupt sources
+  while (((iid = U2IIR) & UIIR_NO_INT) == 0)
+    {
+    // identify & process the highest priority interrupt
+    switch (iid & UIIR_ID_MASK)
+      {
+      case UIIR_RLS_INT:                // Receive Line Status
+        U2LSR;                          // read LSR to clear
+        break;
+
+      case UIIR_CTI_INT:                // Character Timeout Indicator
+      case UIIR_RDA_INT:                // Receive Data Available
+        do
+          {
+          uint16_t temp;
+
+          // calc next insert index & store character
+          temp = (uart2_rx_insert_idx + 1) % UART2_RX_BUFFER_SIZE;
+          uart2_rx_buffer[uart2_rx_insert_idx] = U2RBR;
+
+          // check for more room in queue
+          if (temp != uart2_rx_extract_idx)
+            uart2_rx_insert_idx = temp; // update insert index
+          }
+        while (U2LSR & ULSR_RDR);
+
+        break;
+
+      case UIIR_THRE_INT:               // Transmit Holding Register Empty
+        while (U2LSR & ULSR_THRE)
+          {
+          // check if more data to send
+          if (uart2_tx_insert_idx != uart2_tx_extract_idx)
+            {
+            U2THR = uart2_tx_buffer[uart2_tx_extract_idx++];
+            uart2_tx_extract_idx %= UART2_TX_BUFFER_SIZE;
+            }
+          else
+            {
+            // All data is send (acknownledge this to bus driver)
+            uart2TxFinished();
+            uart2_tx_running = 0;       // clear running flag
+            break;
+            }
+          }
+
+        break;
+
+      default:                          // Unknown
+        U2LSR;
+        U2RBR;
+        break;
+      }
+    }
+
+  VICVectAddr = 0x00000000;             // clear this interrupt from the VIC
+  ISR_EXIT();                           // recover registers and return
+}
+