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update for SWO - hw validation menu integrated

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git-svn-id: https://svn.vbchaos.nl/svn/hsb/trunk@239 05563f52-14a8-4384-a975-3d1654cca0fa
This commit is contained in:
mmi
2017-10-06 07:46:54 +00:00
parent ab3301889c
commit 5105d55089
12 changed files with 143 additions and 84 deletions
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18
S - Software/0 - HSB MRTS Kathode-MCP/3 - Implementation/0 - Code/hsb-mrts/src/stm32f10x_it.c
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@@ -38,6 +38,8 @@
#include "stm32f10x_usart.h"
#include "Display.h"
#include "repairProcess.h"
#include "Logger.h"
#include "platform.h"
#include "rtc.h"
@@ -270,6 +272,8 @@ void EXTI9_5_IRQHandler (void)
extern struct Display* display;
extern struct RepairProcess* rp;
void RTC_IRQHandler(void)
{
static signed portBASE_TYPE higherPriorityTaskWoken = pdFALSE;
@@ -281,10 +285,20 @@ void RTC_IRQHandler(void)
xSemaphoreGiveFromISR(rtc->secondSync, &higherPriorityTaskWoken);
Display_feedRefreshCounter(display);
repairProcess_feedSecondsCounterFromISR(rp);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
portEND_SWITCHING_ISR(higherPriorityTaskWoken);
}
if (RTC_GetITStatus(RTC_IT_OW))
{
// Counter overflow on next cycle pending - RESET counter to 0
RTC_ClearITPendingBit(RTC_IT_OW);
RTC_SetCounter(0x00);
LOGGER_WARNING_ISR(mainLog, "RTC counter overflow detected - reset system clock counter to 0");
}
portEND_SWITCHING_ISR(higherPriorityTaskWoken);
}