Added ferrite core. Cable length is too long.
Photonis is responsible for the design now.

git-svn-id: https://svn.vbchaos.nl/svn/hsb/trunk@406 05563f52-14a8-4384-a975-3d1654cca0fa
This commit is contained in:
tla
2017-12-18 07:40:14 +00:00
parent b6425fe516
commit c6bf5e329f
3 changed files with 47 additions and 6 deletions

View File

@@ -118,8 +118,8 @@ Name=Silk_bottom
Value=No Value=No
[Parameter8] [Parameter8]
Name=MLA Name=Rev
Value=MLA-0387-C4 Value=PA1
[Parameter9] [Parameter9]
Name=Project_Title Name=Project_Title
@@ -130,13 +130,13 @@ Name=PCB_Thickness
Value=1.6 mm Value=1.6 mm
[Parameter11] [Parameter11]
Name=Rev
Value=PA0
[Parameter12]
Name=PCB_Dimension Name=PCB_Dimension
Value=10 x 10 mm Value=10 x 10 mm
[Parameter12]
Name=MLA
Value=MLA-0387-C4
[Parameter13] [Parameter13]
Name=MK_Drawn Name=MK_Drawn
Value=TLa Value=TLa
@@ -786,6 +786,46 @@ OutputName9=Export IDF
OutputDocumentPath9= OutputDocumentPath9=
OutputVariantName9= OutputVariantName9=
OutputDefault9=0 OutputDefault9=0
OutputType10=Ansoft Neutral
OutputName10=Ansoft Neutral (AutoPCB)
OutputDocumentPath10=
OutputVariantName10=
OutputDefault10=0
OutputType11=HyperLynx
OutputName11=HyperLynx (AutoPCB)
OutputDocumentPath11=
OutputVariantName11=
OutputDefault11=0
OutputType12=Orcad SDT Schematic
OutputName12=Orcad SDT Schematic (AutoSCH)
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=Orcad v7 Capture Design
OutputName13=Orcad v7 Capture Design (AutoSCH)
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
OutputType14=P-CAD ASCII
OutputName14=P-CAD ASCII (AutoPCB)
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
OutputType15=P-CAD V16 Schematic Design
OutputName15=P-CAD V16 Schematic Design (AutoSCH)
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=Protel PCB 2.8 ASCII
OutputName16=Protel PCB 2.8 ASCII (AutoPCB)
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=SiSoft
OutputName17=SiSoft (AutoPCB)
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
[OutputGroup10] [OutputGroup10]
Name=PostProcess Outputs Name=PostProcess Outputs
@@ -1055,6 +1095,7 @@ Type110=1
Type111=1 Type111=1
Type112=1 Type112=1
Type113=1 Type113=1
MultiChannelAlternate=2
[ERC Connection Matrix] [ERC Connection Matrix]
L1=NNNNNNNNNNNWNNNWW L1=NNNNNNNNNNNWNNNWW