Rev PA1
Added ferrite core. Cable length is too long. Photonis is responsible for the design now. git-svn-id: https://svn.vbchaos.nl/svn/hsb/trunk@406 05563f52-14a8-4384-a975-3d1654cca0fa
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@@ -118,8 +118,8 @@ Name=Silk_bottom
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Value=No
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[Parameter8]
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Name=MLA
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Value=MLA-0387-C4
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Name=Rev
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Value=PA1
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[Parameter9]
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Name=Project_Title
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@@ -130,13 +130,13 @@ Name=PCB_Thickness
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Value=1.6 mm
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[Parameter11]
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Name=Rev
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Value=PA0
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[Parameter12]
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Name=PCB_Dimension
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Value=10 x 10 mm
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[Parameter12]
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Name=MLA
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Value=MLA-0387-C4
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[Parameter13]
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Name=MK_Drawn
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Value=TLa
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@@ -786,6 +786,46 @@ OutputName9=Export IDF
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OutputDocumentPath9=
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OutputVariantName9=
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OutputDefault9=0
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OutputType10=Ansoft Neutral
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OutputName10=Ansoft Neutral (AutoPCB)
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OutputDocumentPath10=
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OutputVariantName10=
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OutputDefault10=0
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OutputType11=HyperLynx
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OutputName11=HyperLynx (AutoPCB)
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OutputDocumentPath11=
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OutputVariantName11=
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OutputDefault11=0
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OutputType12=Orcad SDT Schematic
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OutputName12=Orcad SDT Schematic (AutoSCH)
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OutputDocumentPath12=
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OutputVariantName12=
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OutputDefault12=0
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OutputType13=Orcad v7 Capture Design
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OutputName13=Orcad v7 Capture Design (AutoSCH)
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OutputDocumentPath13=
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OutputVariantName13=
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OutputDefault13=0
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OutputType14=P-CAD ASCII
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OutputName14=P-CAD ASCII (AutoPCB)
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OutputDocumentPath14=
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OutputVariantName14=
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OutputDefault14=0
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OutputType15=P-CAD V16 Schematic Design
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OutputName15=P-CAD V16 Schematic Design (AutoSCH)
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OutputDocumentPath15=
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OutputVariantName15=
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OutputDefault15=0
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OutputType16=Protel PCB 2.8 ASCII
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OutputName16=Protel PCB 2.8 ASCII (AutoPCB)
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OutputDocumentPath16=
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OutputVariantName16=
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OutputDefault16=0
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OutputType17=SiSoft
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OutputName17=SiSoft (AutoPCB)
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OutputDocumentPath17=
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OutputVariantName17=
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OutputDefault17=0
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[OutputGroup10]
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Name=PostProcess Outputs
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@@ -1055,6 +1095,7 @@ Type110=1
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Type111=1
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Type112=1
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Type113=1
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MultiChannelAlternate=2
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[ERC Connection Matrix]
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L1=NNNNNNNNNNNWNNNWW
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